Content addressable memories (CAMs) can be used within a wealth of different electronic systems (e.g., computing systems such as laptop computers, personal computers (PCs), servers, etc.; networking systems such as routers, switches, base stations, etc.; etc.,). Often, a CAM is used to perform a “look-up” function. For example, in networking applications, a portion of the header information of a packet is often used as a search key or comparand to look-up or identify an entry in the CAM. The address at which the matching entry is located in the CAM can then be used to address or index a location in associated memory where attributes as to how the packet is to be handled are found (e.g., an attribute that identifies the priority level of the packet, an attribute that identifies the specific fiber-optic cable over which the packet is to be launched, etc.).
FIG. 1 shows an example of at least a portion 100 of a CAM architecture. According to the depiction of FIG. 1, CAM architecture 100 includes a plurality (“K”) of rows of CAM cells 1401 through 140K. Each CAM cell includes a memory storage element and a compare circuit and can be binary (i.e., effectively stores and compares on two logic states—logic 0 and logic 1) or ternary (i.e., effectively stores and compares on three logic states—logic 0, logic 1, and a don't care state).
A comparand is typically registered in comparand register 108 and then compared with the data values stored within the plurality of CAM cells 140. The comparison results are reflected as match signals on corresponding match signal lines 1101-110K. The match signals are typically then latched by latch 102. Latch 102 has K latch circuits 1021-102K that each latch a corresponding match signal state in response to the latch enable signal generated by timing generator 103. The latch enable signal is typically generated in response to a cycle clock and control signal CMP that indicates when a compare operation is taking place.
The latched match signals are provided to priority encoder 105 and flag logic 113 over signal lines 1041-104K. Priority encoder 105 processes the match signals in a predetermined manner to determine which of the matching entries (i.e., those data values in the CAM array that match the comparand) is the highest priority matching entry. An index or address of the highest priority matching entry in the CAM array is then output from priority encoder 105 over signal lines 106. Flag logic 113 typically generates a match flag signal that indicates if one or more of the match signals indicates a match, and thus qualifies the output of the priority encoder.
Semiconductor integrated circuit (IC) designers typically specify minimum performance levels that the IC will meet or exceed across a wide range of operating conditions of a CAM device. The operating conditions include environmental conditions (e.g., temperature, moisture content in the operating environment, pressure, etc.), electrical conditions (e.g., supply voltage, input and output voltages, currents and loading, etc.), manufacturing variations (e.g., fabrication variations in transistor geometries and properties, material geometries and properties, etc., which are commonly referred to as “process variations”), and functional considerations (e.g., which operations have been performed by the device and which operations are currently being performed by the device, etc.).
With respect to CAM architecture 100, timing generator 103 is typically designed using simulation tools to transition the latch enable signal at a point in time when all of the match signals are stable after a compare operation. As such, the timing generator is typically designed to transition the latch enable signal to capture accurate match results even under worst case operating conditions. Worst case operating conditions are typically high operating temperature, low supply voltage, slow fabrication geometries, and the slowest time required for CAM array 140 to perform a match and/or a mis-match operation. Although this design approach may guarantee a minimum performance under worst case operating conditions, it sacrifices better performance that could have been realized under better than worst case operating conditions. This can adversely affect the rated performance of the CAM device and can decrease the overall operating frequency, speed or throughput of the device. For example, the longer time that is required to latch the match signals, the later in a particular clock cycle (e.g., of the cycle clock) that it takes for the priority encoder and flag logic to perform their respective operations. This slows down the maximum operating speed of the device.
Additionally, timing generator 103 is typically designed as a pulse generator (e.g., a one-shot) and/or a delay circuit (e.g., one or more inverting or non-inverting buffer circuits or resistor-capacitor (RC) circuits). Since these circuits are designed differently than CAM array 140 (i.e., do not include CAM cells), as operating conditions change the latch enable signal output by timing generator 103 typically does not track in time or voltage proportionally with changes to the match results provided on match lines 110. This variation is further simulated and accounted for during design, and typically results in additional delay added to the point in time at which the latch enable signal is designed to transition.
Like reference numerals refer to corresponding parts throughout the drawing figures.